82NM10 Datasheet, PDF (54/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
Table 2-13.Power Management Interface Signals (Sheet 3 of 3)
Name
BATLOW#
DPRSLPVR
DPRSTP#
Type
Description
Battery Low: This signal is an input from battery to indicate that
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there is insufficient power to boot the system. Assertion will prevent
wake from S3–S5 state. This signal can also be enabled to cause an
SMI# when asserted.
Deeper Sleep - Voltage Regulator: This signal is used to lower the
voltage of VRM during the C4 state. When the signal is high, the
O voltage regulator outputs the lower “Deeper Sleep” voltage. When
low (default), the voltage regulator outputs the higher “Normal”
voltage.
O Deeper Stop: This is a copy of the DPRSLPVR and it is active low.
2.12 Processor Interface
Table 2-14.Processor Interface Signals (Sheet 1 of 2)
Name
Type
Description
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INIT3_3V#
O
Mask A20: A20M# will go active based on either setting the appropriate
bit in the Port 92h register, or based on the A20GATE input being active.
CPU Sleep: This signal puts the processor into a state that saves
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substantial power compared to Stop-Grant state. However, during that
time, no snoops occur. The chipset can optionally assert the CPUSLP#
signal when going to the S1 state.
Numeric Coprocessor Error: This signal is tied to the coprocessor
error signal on the processor. FERR# is only used if the chipset co-
processor error reporting function is enabled in the OIC.CEN register
(Chipset Config Registers:Offset 31FFh: bit 1). If FERR# is asserted, The
chipset generates an internal IRQ13 to its interrupt controller unit. It is
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also used to gate the IGNNE# signal to ensure that IGNNE# is not
asserted to the processor unless FERR# is active. FERR# requires an
external weak pull-up to ensure a high level when the coprocessor error
function is disabled.
NOTE: FERR# can be used in some states for notification by the
processor of pending interrupt events. This functionality is
independent of the OIC register bit setting.
Ignore Numeric Error: This signal is connected to the ignore error pin
on the processor. IGNNE# is only used if The chipset co-processor error
reporting function is enabled in the OIC.CEN register (Chipset Config
O
Registers:Offset 31FFh: bit 1). If FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error register (I/O register
F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until
FERR# is negated. If FERR# is not asserted when the Coprocessor Error
register is written, the IGNNE# signal is not asserted.
Initialization: INIT# is asserted by The chipset for 16 PCI clocks to
O reset the processor. The chipset can be configured to support processor
Built In Self Test (BIST).
O
Initialization 3.3 V: This is the identical 3.3 V copy of INIT# intended
for Firmware Hub.
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