82NM10 Datasheet, PDF (580/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
Bit
Description
1 BITCLK Detected Inverted (CLKDET#) — RO. This bit is modified by hardware.
It is set to 0 when the Chipset detects that the BITCLK is toggling, indicating the
presence of an AC’97 codec on the link.
NOTES:
1.
Bit 2 (CLKDETEN) and bit 3 (CLKDETCLR) in this register control the operation of
this bit and must be manipulated correctly in order to get a valid CLKDET#
indicator.
2.
This bit is not affected by the D3HOT to D0 transition.
0 Intel HD Audio Signal Mode — R/W. This bit selects the Intel High Definition Audio
signals.
0 = Reserved
1 = Intel High Definition Audio mode is selected
NOTES:
1.
This bit has no effect on the visibility of the Intel High Definition Audio function
configuration space.
2.
This bit is in the resume well and only clear on a power-on reset. Software must
not makes assumptions about the reset state of this bit and must set it
appropriately.
18.1.20 TCSEL—Traffic Class Select Register
(Intel HD Audio Controller—D27:F0)
Address Offset: 44h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register assigned the value to be placed in the TC field. CORB and RIRB data will
always be assigned TC0.
Bit
Description
7:3 Reserved.
2:0 Intel HD Audio Traffic Class Assignment (TCSEL)— R/W. This register assigns the
value to be placed in the Traffic Class field for input data, output data, and buffer
descriptor transactions.
000 = TC0
001 = TC1
010 = TC2
011 = TC3
100 = TC4
101 = TC5
110 = TC6
111 = TC7
NOTE: These bits are not reset on D3_HOT to D0 transition; however, they are reset by
PLTRST#.
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Datasheet