82NM10 Datasheet, PDF (492/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.1.37.2 STME—SATA Indexed Registers Index C1h
(SATA Test Mode Enable Register)
Address Offset: Index 1Ch–1Fh
Attribute:
R/W
Default Value: 00000000h
Size:
32 bits
.
Bit
Description
31:19 Reserved.
18 SATA Test Mode Enable Bit — R/W:
0 = Entrance to Chipset SATA test modes are disabled.
1 = This bit allows entrance to Chipset SATA test modes when set.
NOTE: This bit only to be used for system board testing.
17:0 Reserved.
15.1.37.3 STTT2 — SATA Indexed Registers Index 74h
(SATA TX Termination Test Register 2)
Address Offset: Index 74h – 77h
Attribute:
R/W
Default Value: 00000000h
Size:
32 bits
.
Bit
Description
31:18 Reserved.
17 Port 3 TX Termination Test Enable — R/W:
0 = Port 3 TX termination port testing is disabled.
1 = Enables testing of Port 3 TX termination.
NOTE: This bit only to be used for system board testing.
16 Port 2 TX Termination Test Enable — R/W:
0 = Port 2 TX termination port testing is disabled.
1 = Enables testing of Port 2 TX termination.
NOTE: This bit only to be used for system board testing.
15:0 Reserved.
15.1.38 SCAP0—SATA Capability Register 0 (SATA–D31:F2)
Address Offset: A8h–ABh
Default Value: 00100012h
Attribute:
Size:
RO
32 bits
This register is set to 00000000h if the SCRD bit (D31:F2;Offset 94h bit-30) is set.
Bit
Description
31:24
23:20
19:16
Reserved
Major Revision (MAJREV) — RO: Major revision number of the SATA Capability Pointer
implemented.
Minor Revision (MINREV) — RO: Minor revision number of the SATA Capability Pointer
implemented.
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Datasheet