82NM10 Datasheet, PDF (55/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
Table 2-14.Processor Interface Signals (Sheet 2 of 2)
Name
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPUPWRGD
/ GPIO49
DPSLP#
Type
Description
CPU Interrupt: INTR is asserted by the chipset to signal the processor
O that an interrupt request is pending and needs to be serviced. It is an
asynchronous output and normally driven low.
Non-Maskable Interrupt: NMI is used to force a non-Maskable
interrupt to the processor. The chipset can generate an NMI when either
O
SERR# is asserted or IOCHK# goes active via the SERIRQ# stream. The
processor detects an NMI when it detects a rising edge on NMI. NMI is
reset by setting the corresponding NMI source enable/disable bit in the
NMI Status and Control register (I/O Register 61h).
System Management Interrupt: SMI# is an active low output
O synchronous to PCICLK. It is asserted by the chipset in response to one
of many enabled hardware or software events.
Stop Clock Request: STPCLK# is an active low output synchronous to
O
PCICLK. It is asserted by the chipset in response to one of many
hardware or software events. When the processor samples STPCLK#
asserted, it responds by stopping its internal clock.
Keyboard Controller Reset CPU: The keyboard controller can
generate INIT# to the processor. This saves the external OR gate with
I
the chipset’s other sources of INIT#. When the chipset detects the
assertion of this signal, INIT# is generated for 16 PCI clocks.
NOTE: The chipset will ignore RCIN# assertion during transitions to the
S1, S3, S4, and S5 states.
A20 Gate: A20GATE is from the keyboard controller. The signal acts as
I an alternative method to force the A20M# signal active. It saves the
external OR gate needed with various other chipsets.
CPU Power Good: This signal should be connected to the processor’s
PWRGOOD input to indicate when the CPU power is valid. This is an
O ^{output signal that represents a logical AND of the chipset’s PWROK and}
VRMPWRGD signals.
This signal may optionally be configured as a GPIO.
Deeper Sleep: DPSLP# is asserted by the chipset to the processor.
O
When the signal is low, the processor enters the deep sleep state by
gating off the processor core clock inside the processor. When the signal
is high (default), the processor is not in the deep sleep state.
2.13 SMBus Interface
Table 2-15.SM Bus Interface Signals
Name
Type
Description
SMBDATA
SMBCLK
SMBALERT# /
GPIO11
I/OD
I/OD
I
SMBus Data: External pull-up resistor is required.
SMBus Clock: External pull-up resistor is required.
SMBus Alert: This signal is used to wake the system or generate
SMI#. If not used for SMBALERT#, it can be used as a GPIO.
Datasheet
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