82NM10 Datasheet, PDF (305/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.1.11 CSR_MEM_BASE — CSR Memory-Mapped Base
Address Register (LAN Controller—B1:D8:F0)
Offset Address: 10h–13h
Default Value: 00000008h
Attribute:
Size:
R/W, RO
32 bits
Note:
The chipset’s integrated LAN controller requires one BAR for memory mapping.
Software determines which BAR (memory or I/O) is used to access the LAN controller’s
CSR registers.
Bit
Description
31:12 Base Address (MEM_ADDR) — R/W. This field contains the upper 20 bits of the base
address provides 4 KB of memory-Mapped space for the LAN controller’s Control/Status
registers.
11:4 Reserved
3 Prefetchable (MEM_PF) — RO. Hardwired to 0 to indicate that this is not a pre-
fetchable memory-Mapped address range.
2:1 Type (MEM_TYPE) — RO. Hardwired to 00b to indicate the memory-Mapped address
range may be located anywhere in 32-bit address space.
0 Memory-Space Indicator (MEM_SPACE) — RO. Hardwired to 0 to indicate that this
base address maps to memory space.
11.1.12 CSR_IO_BASE — CSR I/O-Mapped Base Address Register
(LAN Controller—B1:D8:F0)
Offset Address: 14h–17h
Default Value: 00000001h
Attribute:
Size:
R/W, RO
32 bits
Note:
The chipset’s integrated LAN controller requires one BAR for memory mapping.
Software determines which BAR (memory or I/O) is used to access the LAN controller’s
CSR registers.
Bit
Description
31:16 Reserved
15:6
5:1
0
Base Address (IO_ADDR)— R/W. This field provides 64 bytes of I/O-Mapped address
space for the LAN controller’s Control/Status registers.
Reserved
I/O Space Indicator (IO_SPACE) — RO. Hardwired to 1 to indicate that this base
address maps to
I/O space.
Datasheet
305