82NM10 Datasheet, PDF (403/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.7.2
Note:
NMI_EN—NMI Enable (and Real Time Clock Index)
Register (LPC I/F—D31:F0)
I/O Address: 70h
Default Value: 80h
Lockable:
No
Attribute:
Size:
Power Well:
R/W (special)
8-bit
Core
The RTC Index field is write-only for normal operation. This field can only be read in Alt-
Access Mode. Note, however, that this register is aliased to Port 74h (documented in),
and all bits are readable at that address.
13.7.3
13.7.4
Bits
Description
7 NMI Enable (NMI_EN) — R/W (special).
0 = Enable NMI sources.
1 = Disable All NMI sources.
6:0 Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to
the RTC to select which register or CMOS RAM address is being accessed.
PORT92—Fast A20 and Init Register (LPC I/F—D31:F0)
I/O Address: 92h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:2 Reserved
1 Alternate A20 Gate (ALT_A20_GATE) — R/W. This bit is Or’d with the A20GATE
input signal to generate A20M# to the processor.
0 = A20M# signal can potentially go active.
1 = This bit is set when INIT# goes active.
0 INIT_NOW — R/W. When this bit transitions from a 0 to a 1, the Chipset will force
INIT# active for 16 PCI clocks.
COPROC_ERR—Coprocessor Error Register
(LPC I/F—D31:F0)
I/O Address: F0h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bits
Core
Bits
Description
7:0 Coprocessor Error (COPROC_ERR) — R/W. Any value written to this register will
cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to
generate an internal IRQ13, the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0,
Bit 13) must be 1. Reads to this register always return 00h.
Datasheet
403