82NM10 Datasheet, PDF (213/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.22.4
Flash Protection
There are three types of Flash Protection mechanisms:
1. BIOS Range Write Protection
2. SMI#-Based Global Write Protection
The three mechanisms are conceptually OR’d together such that if any of the
mechanisms indicate that the access should be blocked, then it is blocked. Table 5-88
provides a summary of the Three Mechanisms.
Table 5-88.Flash Protection Mechanism Summary
Mechanism
Accesses
Blocked
BIOS Range
Write
Protection
Write Protect
Writes
Writes
BIOS BAR
Reads and
Writes
Range Reset-Override
Specific
or SMI#-
Equivalent Function on FWH
?
Override?
Yes
Reset Override FWH Sector Protection
No
SMI# Override Same as Write Protect in
previous ICH components for
FWH
Yes
Reset Override Not Applicable- Specific to
Flash Sharing
A blocked command will appear to software to finish, except that the Blocked Access
status bit is set in this case.
5.22.4.1
Note:
BIOS Range Write Protection
Chipset provides a method for blocking writes to specific ranges in the SPI flash when
the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type
information (which can be locked down by the initial Boot BIOS) and the address of the
requested command against the base and limit fields of a Write Protected BIOS range.
Once BIOS has locked down the Protected BIOS Range registers, this mechanism
remains in place until the next system reset.
5.22.4.2
SMI# Based Global Write Protection
Chipset provides a method for blocking writes to the SPI flash when the Write Protect
bit is cleared (i.e., protected). This is achieved by checking the Opcode type
information (which can be locked down by the initial Boot BIOS) of the requested
command.
The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as
they do for the FWH BIOS.
Datasheet
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