82NM10 Datasheet, PDF (196/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
indicates a Transaction Error), then the attached device is not a debug peripheral. If the
debug port peripheral is not present, then debug software may choose to terminate or
it may choose to wait until a debug peripheral is connected.
5.20
SMBus Controller (D31:F3)
Chipset provides an System Management Bus (SMBus) 2.0 host controller as well as an
SMBus Slave Interface. The host controller provides a mechanism for the processor to
initiate communications with SMBus peripherals (slaves). Chipset is also capable of
operating in a mode in which it can communicate with I²C compatible devices.
Chipset can perform SMBus messages with either packet error checking (PEC) enabled
or disabled. The actual PEC calculation and checking is performed in hardware by
Chipset.
The Slave Interface allows an external master to read from or write to Chipset. Write
cycles can be used to cause certain events or pass messages, and the read cycles can
be used to determine the state of various status bits. Chipset’s internal host controller
cannot access chipset’s internal Slave Interface.
Chipset SMBus logic exists in Device 31:Function 3 configuration space, and consists of
a transmit data path, and host controller. The transmit data path provides the data flow
logic needed to implement the seven different SMBus command protocols and is
controlled by the host controller. Chipset SMBus controller logic is clocked by RTC clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host
controller commands through software, except for the new Host Notify command
(which is actually a received message).
The programming model of the host controller is combined into two portions: a PCI
configuration portion, and a system I/O mapped portion. All static configuration, such
as the I/O base address, is done via the PCI configuration space. Real-time
programming of the Host interface is done in system I/O space.
Chipset SMBus host controller checks for parity errors as a target. If an error is
detected, the detected parity error bit in the PCI Status Register (Device 31:Function
3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device
31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit
in the PCI Status Register (bit 14) is set.
5.20.1
Host Controller
The SMBus host controller is used to send commands to other SMBus slave devices.
Software sets up the host controller with an address, command, and, for writes, data
and optional PEC; and then tells the controller to start. When the controller has finished
transmitting data on writes, or receiving data on reads, it generates an SMI# or
interrupt, if enabled.
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Datasheet