82NM10 Datasheet, PDF (151/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.14.9.4
5.14.9.5
SYS_RESET# Signal
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic,
Chipset attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus
to go idle. If the SMBus is idle when the pin is detected active, the reset occurs
immediately; otherwise, the counter starts. If at any point during the count the SMBus
goes idle the reset occurs. If, however, the counter expires and the SMBus is still active,
a reset is forced upon the system even though activity is still occurring.
Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the
SYS_RESET# input remains asserted or not. It cannot occur again until SYS_RESET#
has been detected inactive after the debounce logic, and the system is back to a full S0
state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then
SYS_RESET# will result in a full power cycle reset.
THRMTRIP# Signal
If THRMTRIP# goes active, the processor is indicating an overheat condition, and
Chipset immediately transitions to an S5 state. However, since the processor has
overheated, it does not respond to chipset’s STPCLK# pin with a stop grant special
cycle. Therefore, Chipset does not wait for one. Immediately upon seeing THRMTRIP#
low, Chipset initiates a transition to the S5 state, drive SLP_S3#, SLP_S4#, SLP_S5#
low, and set the CTS bit. The transition looks like a power button override.
It is extremely important that when a THRMTRIP# event occurs, Chipset power down
immediately without following the normal S0 -> S5 path. This path may be taken in
parallel, but Chipset must immediately enter a power down state. It does this by
driving SLP_S3#, SLP_S4#, and SLP_S5# immediately after sampling THRMTRIP#
active.
If the processor is running extremely hot and is heating up, it is possible (although very
unlikely) that components around it, such as Chipset, are no longer executing cycles
properly. Therefore, if THRMTRIP# goes active, and Chipset is relying on state machine
logic to perform the power down, the state machine may not be working, and the
system will not power down.
Chipset follows this flow for THRMTRIP#.
1. At boot (PLTRST# low), THRMTRIP# ignored.
2. After power-up (PLTRST# high), if THRMTRIP# sampled active, SLP_S3#,
SLP_S4#, and SLP_S5# assert, and normal sequence of sleep machine starts.
3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay
active, even if THRMTRIP# is now inactive. This is the equivalent of “latching” the
thermal trip event.
4. If S5 state reached, go to step #1, otherwise stay here. If Chipset does not reach
S5, Chipset does not reboot until power is cycled.
Datasheet
151