82NM10 Datasheet, PDF (544/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
Note:
value of SOFV must be kept consistent if chip is reset or software writes to FRINDEX.
Writes to FRINDEX must also
write-through FRINDEX[13:3] to SOFV[10:0]. In order to keep the update as simple
as possible, software should not write a FRINDEX value where the three least
significant bits are 111b or 000b.
This register is used by the host controller to index into the periodic frame list. The
register updates every 125 microseconds (once each micro-frame). Bits [12:3] are
used to select a particular entry in the Periodic Frame List during periodic schedule
execution. The number of bits used for the index is fixed at 10 for the Chipset since it
only supports 1024-entry frame lists. This register must be written as a DWord. Word
and byte writes produce undefined results. This register cannot be written unless the
Host controller is in the Halted state as indicated by the HCHalted bit
(D29:F7:CAPLENGTH + 24h, bit 12). A write to this register while the Run/Stop bit
(D29:F7:CAPLENGTH + 20h, bit 0) is set to a 1 (USB2.0_CMD register) produces
undefined results. Writes to this register also effect the SOF value. See Section 4 of the
EHCI specification for details.
16.2.2.5
Bit
Description
31:14 Reserved
13:0
Frame List Current Index/Frame Number — R/W. The value in this register
increments at the end of each time frame (e.g., micro-frame).
Bits [12:3] are used for the Frame List current index. This means that each location of
the frame list is accessed 8 times (frames or micro-frames) before moving to the next
index.
CTRLDSSEGMENT—Control Data Structure Segment
Register
Offset:
MEM_BASE + 30h–33h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
This 32-bit register corresponds to the most significant address bits [63:32] for all
EHCI data structures. Since the Chipset hardwires the 64-bit Addressing Capability field
in HCCPARAMS to 1, then this register is used with the link pointers to construct 64-bit
addresses to EHCI control data structures. This register is concatenated with the link
pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data
structure link field to construct a 64-bit address. This register allows the host software
to locate all control data structures within the same 4 GB memory segment.
Bit
Description
31:12 Upper Address[63:44] — RO. Hardwired to 0s. The Chipset EHC is only capable of
generating addresses up to 16 terabytes (44 bits of address).
11:0 Upper Address[43:32] — R/W. This 12-bit field corresponds to address bits 43:32
when forming a control data structure address.
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Datasheet