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82NM10 Datasheet, PDF (380/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset | |||
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LPC Interface Bridge Registers (D31:F0)
13.2.8
DMA Clear Byte Pointer Register (LPC I/FâD31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0â3 = 0Ch;
Ch. #4â7 = D8h
xxxx xxxx
No
Attribute:
Size:
Power Well:
WO
8-bit
Core
Bit
Description
7:0 Clear Byte Pointer â WO. No specific pattern. Command enabled with a write to the
I/O port address. Writing to this register initializes the byte pointer flip/flop to a known
state. It clears the internal latch used to address the upper or lower byte of the 16-bit
Address and Word Count Registers. The latch is also cleared by part reset and by the
Master Clear command. This command precedes the first access to a 16-bit DMA
controller register. The first access to a 16-bit register will then access the significant
byte, and the second access automatically accesses the most significant byte.
13.2.9
DMA Master Clear Register (LPC I/FâD31:F0)
I/O Address:
Default Value:
Ch. #0â3 = 0Dh;
Ch. #4â7 = DAh
xxxx xxxx
Attribute:
Size:
WO
8-bit
Bit
Description
7:0 Master Clear â WO. No specific pattern. Enabled with a write to the port. This has the
same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer
flip/flop registers are cleared and the Mask Register is set.
13.2.10 DMA_CLMSKâDMA Clear Mask Register (LPC I/FâD31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0â3 = 0Eh;
Ch. #4â7 = DCh
xxxx xxxx
No
Attribute:
Size:
Power Well:
WO
8-bit
Core
Bit
Description
7:0 Clear Mask Register â WO. No specific pattern. Command enabled with a write to the
port.
380
Datasheet
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