82NM10 Datasheet, PDF (187/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
• Netbook systems may want to minimize the conditions that will wake the system.
Chipset implements the “Wake Enable” bits in the Port Status and Control registers,
as specified in the EHCI spec, for this purpose.
• Netbook systems may want to cut suspend well power to some or all USB ports
when in a low-power state. Chipset implements the optional Port Wake Capability
Register in the EHC Configuration Space for this platform-specific information to be
communicated to software.
5.19.8
5.19.8.1
Interaction with UHCI Host Controllers
The Enhanced Host controller shares the eight USB ports with four UHCI Host
controllers in Chipset. The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1
shares ports 2 and 3; the UHC at D29:F2 shares ports 4 and 5; and the UHC at D29:F3
shares ports 6 and 7 with the EHC. There is very little interaction between the
Enhanced and the UHCI controllers other than the muxing control which is provided as
part of the EHC.Figure 5-15 shows the USB Port Connections at a conceptual level.
Port-Routing Logic
Integrated into the EHC functionality is port-routing logic, which performs the muxing
between the UHCI and EHCI host controllers. Chipset conceptually implements this
logic as described in Section 4.2 of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0. If a device is connected that is not capable of
USB 2.0’s high-speed signaling protocol or if the EHCI software drivers are not present
as indicated by the Configured Flag, then the UHCI controller owns the port. Owning
the port means that the differential output is driven by the owner and the input stream
is only visible to the owner. The host controller that is not the owner of the port
internally sees a disconnected port.
Datasheet
187