82NM10 Datasheet, PDF (257/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Register and Memory Mapping
Note:
SMBus controller. D29 contains the four USB UHCI controllers and one USB EHCI
controller. D27 contains the Intel High Definition Audio controller. B1:D8 is the
integrated LAN controller.
From a software perspective, the integrated LAN controller resides on the Chipset's
external PCI bus. This is typically Bus 1, but may be assigned a different number
depending on system configuration.
If for some reason, the particular system platform does not want to support any one of
the Device Functions, with the exception of D30:F0, they can individually be disabled.
The integrated LAN controller will be disabled if no Platform LAN Connect component is
detected (See Chapter 5.3 - Volume 1). When a function is disabled, it does not appear
at all to the software. A disabled function will not respond to any register reads or
writes, insuring that these devices appear hidden to software.
b
Table 9-106.PCI Devices and Functions
Bus:Device:Function¹
Function Description
Bus 0:Device 30:Function 0
Bus 0:Device 31:Function 0
Bus 0:Device 31:Function 2
Bus 0:Device 31:Function 3
Bus 0:Device 29:Function 0
Bus 0:Device 29:Function 1
Bus 0:Device 29:Function 2
Bus 0:Device 29:Function 3
Bus 0:Device 29:Function 7
Bus 0:Device 28:Function 0
Bus 0:Device 28:Function 1
Bus 0:Device 28:Function 2
Bus 0:Device 28:Function 3
Bus 0:Device 27:Function 0
Bus n:Device 8:Function 0
PCI-to-PCI Bridge
LPC Controller¹
SATA Controller
SMBus Controller
USB UHCI Controller #1
USB UHCI Controller #2
USB UHCI Controller #3
USB UHCI Controller #4
USB 2.0 EHCI Controller
PCI Express* Port 1
PCI Express Port 2
PCI Express Port 3
PCI Express Port 4
Intel HD Audio Controller
LAN Controller
NOTES:
1.
The LPC controller contains registers that control LPC, Power Management, System
Management, GPIO, processor Interface, RTC, Interrupts, Timers, DMA.
9.2
PCI Configuration Map
Each PCI function on the Chipset has a set of PCI configuration registers. The register
address map tables for these register sets are included at the beginning of the chapter
for the particular function. Configuration Space registers are accessed through
configuration cycles on the PCI bus by the Host bridge using configuration mechanism
#1 detailed in the PCI Local Bus Specification, Revision 2.3.
Datasheet
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