82NM10 Datasheet, PDF (293/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
10.1.49 HPTC—High Precision Timer Configuration Register
Offset Address: 3404–3407h
Default Value: 00000000h
Attribute:
Size:
R/W
32-bit
Bit
Description
31:8
7
6:2
1:0
Reserved
Address Enable (AE) — R/W.
0 = Address disabled.
1 = The Chipset will decode the High Precision Timer memory address range selected
by bits 1:0 below.
Reserved
Address Select (AS) — R/W. This field selects 1 of 4 possible memory address
ranges for the High Precision Timer functionality. The encodings are:
00 = FED0_0000h – FED0_03FFh
01 = FED0_1000h – FED0_13FFh
10 = FED0_2000h – FED0_23FFh
11 = FED0_3000h – FED0_33FFh
10.1.50 GCS—General Control and Status Register
Bit
31:12
11:10
Offset Address: 3410–3413h
Attribute:R/W, R/WLO
Default Value: 00000yy0h (yy = xx0000x0b)Size: 32-bit
Description
Reserved
Boot BIOS Straps (BBS): This field determines the destination of accesses to the BIOS memory
range. The default values for these bits represent the strap values of GNT5#/GPIO17 (bit 11) and
GNT4#/GPIO48 (bit 10) (active-high logic levels) at the rising edge of PWROK.
Bits 11:10
00b
01b
10b
11b
Description
Reserved
SPI (supports shared flash with LAN)
PCI
LPC
When PCI is selected, the top 16 MB of memory below 4 GB (FF00_0000h to FFFF_FFFFh) is
accepted by the primary side of the PCI-to-PCI bridge and forwarded to the PCI bus. This allows
systems with corrupted or unprogrammed flash to boot from a PCI device. The PCI-to-PCI bridge
Memory Space Enable bit does not need to be set (nor any other bits) for these cycles to go to PCI.
Note that BIOS decode range bits and the other BIOS protection bits have no effect when PCI is
selected.
When SPI or LPC is selected, the range that is decoded is further qualified by other configuration
bits described in the respective sections.
The value in this field can be overwritten by software as long as the BIOS Interface Lock-Down (bit
0) is not set.
Datasheet
293