82NM10 Datasheet, PDF (408/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.8.1.3
Bit
Description
0 PWROK Failure (PWROK_FLR) — R/WC.
0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3
state.
1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1
state. The bit will be cleared only by software by writing a 1 to this bit or when the
system goes to a G3 state.
NOTE: See Chapter 5.14.11.3 - Volume 1 for more details about the PWROK pin
functionality.
NOTE: In the case of true PWROK failure, PWROK will go low first before the
VRMPWRGD.
NOTE: VRMPWROK is sampled using the RTC clock. Therefore, low times that are less than one
RTC clock period may not be detected by the Chipset.
GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0)
Offset Address: A4h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, R/WC
8-bit
ACPI, Legacy
RTC
Bit
Description
7:6 _{SWSMI_RATE_SEL — R/W. This field indicates when the SWSMI timer will time out.}
Valid values are:
00 = 1.5 ms ± 0.6 ms
01 = 16 ms ± 4 ms
10 = 32 ms ± 4 ms
11 = 64 ms ± 4 ms
These bits are not cleared by any type of reset except RTCRST#.
5:4 SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum assertion
width of the SLP_S4# signal to ensure that the DRAMs have been safely power-cycled.
Valid values are:
11 = 1 to 2 seconds
10 = 2 to 3 seconds
01 = 3 to 4 seconds
00 = 4 to 5 seconds
This value is used in two ways:
1.
If the SLP_S4# assertion width is ever shorter than this time, a status bit is set
for BIOS to read when S0 is entered.
2.
If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal
from deasserting within this minimum time period after asserting.
RTCRST# forces this field to the conservative default state (00b)
3 SLP_S4# Assertion Stretch Enable — R/W.
0 = The SLP_S4# minimum assertion time is 1 to 2 RTCCLK.
1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this
register.
This bit is cleared by RTCRST#
2 RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RTCRST# indicates
a weak or missing battery. The bit is not cleared by any type of reset. The bit will
remain set until the software clears it by writing a 0 back to this bit position.
408
Datasheet