82NM10 Datasheet, PDF (546/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
16.2.2.8
16.2.2.9
CONFIGFLAG—Configure Flag Register
Offset:
MEM_BASE + 60h–63h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset.
Bit
31:1
0
Description
Reserved. Read from this field will always return 0.
Configure Flag (CF) — R/W. Host software sets this bit as the last action in its process
of configuring the Host controller. This bit controls the default port-routing control logic.
Bit values and side-effects are listed below. See section 4 of the EHCI spec for
operation details.
0 = Port routing control logic default-routes each port to the classic host controllers
(default).
1 = Port routing control logic default-routes all ports to this host controller.
PORTSC—Port N Status and Control Register
Offset:
Attribute:
Default Value:
Port 0: MEM_BASE + 64h–67h
Port 1: MEM_BASE + 68–6Bh
Port 2: MEM_BASE + 6C–6Fh
Port 3: MEM_BASE + 70–73h
Port 4: MEM_BASE + 74–77h
Port 5: MEM_BASE + 78–7Bh
Port 6: MEM_BASE + 7C–7Fh
Port 7: MEM_BASE + 80–83h
R/W, R/WC, RO
00003000h
Size:
32 bits
A host controller must implement one or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
• No device connected
• Port disabled.
When a device is attached, the port state transitions to the attached state and system
software will process this as with any status change notification. Refer to Section 4 of
the EHCI specification for operational requirements for how change events interact with
port suspend mode.
Bit
Description
31:23 Reserved. These bits are reserved for future use and will return a value of 0’s when
read.
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