82NM10 Datasheet, PDF (528/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
16.1.25 PWAKE_CAP—Port Wake Capability Register
(USB EHCI—D29:F7)
Address Offset: 62–63h
Default Value: 01FFh
Attribute:
Size:
R/W
16 bits
This register is in the suspend power well. The intended use of this register is to
establish a policy about which ports are to be used for wake events. Bit positions 1–8 in
the mask correspond to a physical port implemented on the current EHCI controller. A 1
in a bit position indicates that a device connected below the port can be enabled as a
wake-up device and the port may be enabled for disconnect/connect or overcurrent
events as wake-up events. This is an information-only mask register. The bits in this
register do not affect the actual operation of the EHCI host controller. The system-
specific policy can be established by BIOS initializing this register to a system-specific
value. System software uses the information in this register when enabling devices and
ports for remote wake-up.
These bits are not reset by a D3-to-D0 warm rest or a core well reset.
Bit
Description
15:9
8:1
Reserved — RO.
Port Wake Up Capability Mask — R/W. Bit positions 1 through 8 correspond to a
physical port implemented on this host controller. For example, bit position 1
corresponds to port 0, bit position 2 corresponds to port 1, etc.
0 Port Wake Implemented — R/W. A 1 in this bit indicates that this register is
implemented to software.
16.1.26 LEG_EXT_CAP—USB EHCI Legacy Support Extended
Capability Register (USB EHCI—D29:F7)
Address Offset: 68–6Bh
Attribute:
R/W, RO
Default Value: 00000001h
Size:
32 bits
Power Well:
Suspend
NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
Bit
Description
31:25 Reserved — RO. Hardwired to 00h
24 HC OS Owned Semaphore — R/W. System software sets this bit to request ownership
of the EHCI controller. Ownership is obtained when this bit reads as 1 and the HC BIOS
Owned Semaphore bit reads as clear.
23:17 Reserved — RO. Hardwired to 00h
16 HC BIOS Owned Semaphore — R/W. The BIOS sets this bit to establish ownership of
the EHCI controller. System BIOS will clear this bit in response to a request for
ownership of the EHCI controller by system software.
15:8 Next EHCI Capability Pointer — RO. Hardwired to 00h to indicate that there are no
EHCI Extended Capability structures in this device.
7:0 Capability ID — RO. Hardwired to 01h to indicate that this EHCI Extended Capability is
the Legacy Support Capability.
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Datasheet