82NM10 Datasheet, PDF (93/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Dx>0 Power State: While Chipset is in a powerdown state, it may receive TCO
packets or all directly to the TCO controller. Receiving TCO packets is enabled by the set
Receive enable command from the TCO controller. Although TCO packet might match
one of the other wake up filters, once it is transferred to the TCO controller, no further
matching is searched for and PME is not issued. While receive to TCO is not enabled, a
TCO packet may cause a PME if configured to do so (setting TCO to 1 in the filter type).
D0 Power State: At D0 power state, Chipset may transfer TCO packets to the TCO
controller. At this state, TCO packets are posted first to the host memory, then read by
Chipset, and then posted back to the TCO controller. After the packet is posted to TCO,
the receive memory structure (that is occupied by the TCO packet) is reclaimed. Other
than providing the necessary receive resources, there is no required device driver
intervention with this process. Eventually, Chipset increments the receive TCO static
counter, clears the TCO request bit, and resumes normal control.
Read Chipset Status (PM and Link State)
The TCO controller is capable of reading Chipset power state and link status. Following
a status change, Chipset asserts LINKALERT# and then the TCO can read its new power
state.
Set Force TCO Mode
The TCO controller put Chipset into the Force TCO mode. Chipset is set back to the
nominal operation following a PCIRST#. Following the transition from nominal mode to
a TCO mode, Chipset aborts transmission and reception and loses its memory
structures. The TCO may configure Chipset before it starts transmission and reception
if required.
Warning:
The Force TCO is a destructive command. It causes Chipset to lose its memory
structures, and during the Force TCO mode Chipset ignores any PCI accesses.
Therefore, it is highly recommended to use this command by the TCO controller at
system emergency only.
5.4
Alert Standard Format (ASF)
The ASF controller collects information from various components in the system
(including the processor, chipset, BIOS, and sensors on the motherboard) and sends
this information via the LAN controller to a remote server running a management
console. The controller also accepts commands back from the management console
and drives the execution of those commands on the local system.
The ASF controller is responsible for monitoring sensor devices and sending packets
through the LAN controller SMBus (System Management Bus) interface. These ASF
controller alerting capabilities include system health information such as BIOS
messages, POST alerts, operating system failure notifications, and heartbeat signals to
indicate the system is accessible to the server. Also included are environmental
notification (e.g., thermal, voltage and fan alerts) that send proactive warnings that
something is wrong with the hardware. The packets are used as Alert (S.O.S.) packets
Datasheet
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