82NM10 Datasheet, PDF (249/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Electrical Characteristics
Figure 8-36. S0 to S1 to S0 Timing (Nettop Only)
STATE
S0
STPCLK#
DMI Message
CPUSLP#
Wake Event
S0 S1
t280
t281
S1
S1 S0
S0
t301
t271
Figure 8-37. S0 to S5 to S0 Timings, S3_COLD (Nettop Only)
S0
S0 S3
S3 S4
S5
S4 S3
S3/S4/S5 S0
S0
STPCLK#
DMI Message
SUS_STA T#
PLTRST#
SLP_S3#
(S3_COLD Conf ig)
SLP_S4#
SLP_S5#
Wake Event
t280
t283
t284
t287
t291
t295
t215 ( f rom
V _CPU_IO)
t300
t299
t298
t297
t296
t217
t218
V RMPWRGD
PW RO K
V c c¹
t289
t294
t214
ICH7_S0_S5_S0_DT _S3COLD.vsd
NOTES:
1.
Vcc includes Vcc1_5, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL, VccSATAPLL, and V5REF.
2. t294 is applicable when the system transitions from S0 to G3 only.
Datasheet
249