82NM10 Datasheet, PDF (480/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Bit
Description
2 Drive 0 Prefetch/Posting Enable (PPE0) — R/W.
0 = Disable prefetch and posting to the IDE data port for this drive.
1 = Enable prefetch and posting to the IDE data port for this drive.
1 Drive 0 IORDY Sample Point Enable (IE0) — R/W.
0 = Disable IORDY sampling is disabled for this drive.
1 = Enable IORDY sampling for this drive.
0 Drive 0 Fast Timing Bank (TIME0) — R/W.
0 = Accesses to the data port will use compatible timings for this drive.
1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits
9:8 for the recovery time
15.1.22 IDE_TIMS — Slave IDE Timing Register (SATA–D31:F2)
Address Offset: 44h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Note:
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation unless otherwise noted.
Bit
Description
7:6 Secondary Drive 1 IORDY Sample Point (SISP1) — R/W. This field determines the
number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample
point, if the access is to drive 1 data port and bit 14 of the IDE timing register for
secondary is set.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
5:4 Secondary Drive 1 Recovery Time (SRCT1) — R/W. This field determines the
minimum number of PCI clocks between the last IORDY sample point and the IOR#/
IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE
timing register for secondary is set.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
3:2 Primary Drive 1 IORDY Sample Point (PISP1) — R/W. This field determines the
number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample point,
if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is
set.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
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Datasheet