82NM10 Datasheet, PDF (107/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.7.4
5.7.5
5.7.6
— Chipset drives the first 8 bits of data and turns the bus around.
— The peripheral acknowledges the data with a valid SYNC.
— If a 16-bit transfer, the process is repeated for the next 8 bits.
6. If a DMA write -
— Chipset turns the bus around and waits for data.
— The peripheral indicates data ready through SYNC and transfers the first byte.
— If a 16-bit transfer, the peripheral indicates data ready and transfers the next
byte.
7. The peripheral turns around the bus.
Terminal Count
Terminal count is communicated through LAD[3] on the same clock that DMA channel is
communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates
the last byte of transfer, based upon the size of the transfer.
For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is
the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the
second byte is the last byte. The peripheral, therefore, must internalize the TC bit when
the CHANNEL field is communicated, and only signal TC when the last byte of that
transfer size has been transferred.
Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is
similar to a DMA write, where the peripheral is transferring data to main memory. The
indication from the host is the same as a DMA write, so the peripheral will be driving
data onto the LPC interface. However, the host will not transfer this data into main
memory.
DMA Request Deassertion
An end of transfer is communicated to Chipset through a special SYNC field transmitted
by the peripheral. An LPC device must not attempt to signal the end of a transfer by
deasserting LDREQ#. If a DMA transfer is several bytes (e.g., a transfer from a demand
mode device) Chipset needs to know when to deassert the DMA request based on the
data currently being transferred.
The DMA agent uses a SYNC encoding on each byte of data being transferred, which
indicates to Chipset whether this is the last byte of transfer or if more bytes are
requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of
0000b (ready with no error), or 1010b
(ready with error). These encodings tell Chipset that this is the last piece of data
transferred on a DMA read (Chipset to peripheral), or the byte that follows is the last
piece of data transferred on a DMA write (peripheral to Chipset).
Datasheet
107