82NM10 Datasheet, PDF (310/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.1.24 PCIDATA — PCI Power Management Data Register
(LAN Controller—B1:D8:F0)
Offset Address: E3h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Power Management Data (PWR_MGT) — RO. State dependent power consumption
and heat dissipation data.
The data register is an 8-bit read only register that provides a mechanism for the
chipset’s integrated LAN controller to report state dependent maximum power
consumption and heat dissipation. The value reported in this register depends on the
value written to the Data Select field in the PMCSR register. The power measurements
defined in this register have a dynamic range of 0 W to 2.55 W with 0.01 W resolution,
scaled according to the Data Scale field in the PMCSR. The structure of the Data
Register is given in Table 11-113.
Table 11-113.Data Register Structure
Data Select
Data Scale
Data Reported
0
1
2
3
4
5
6
7
8
9–15
2
D0 Power Consumption
2
D1 Power Consumption
2
D2 Power Consumption
2
D3 Power Consumption
2
D0 Power Dissipated
2
D1 Power Dissipated
2
D2 Power Dissipated
2
D3 Power Dissipated
2
Common Function Power
Dissipated
0
Reserved
11.2
LAN Control / Status Registers (CSR)
(LAN Controller—B1:D8:F0)
Table 11-114.Chipset Integrated LAN Controller CSR Space Register Address Map
Offset
00h–01h
02h–03h
04h–07h
Mnemonic
Register Name
SCB_STA System Control Block Status Word
SCB_CMD
SCB_GENPNT
System Control Block Command
Word
System Control Block General
Pointer
Default
0000h
0000h
0000 0000h
Type
R/WC, RO
R/W, WO
R/W
310
Datasheet