82NM10 Datasheet, PDF (671/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Serial Peripheral Interface (SPI)
environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.
21.1.9
Bit
Description
63:56 Allowable Opcode 7 — R/W. See the description for bits 7:0
55:48 Allowable Opcode 6 — R/W. See the description for bits 7:0
47:40 Allowable Opcode 5 — R/W. See the description for bits 7:0
39:32 Allowable Opcode 4 — R/W. See the description for bits 7:0
31:24 Allowable Opcode 3 — R/W. See the description for bits 7:0
23:16 Allowable Opcode 2 — R/W. See the description for bits 7:0
15:8 Allowable Opcode 1 — R/W. See the description for bits 7:0
7:0 Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use
when initiating SPI commands through the Control Register.
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15)
is set.
PBR[N]—Protected BIOS Range [N]
(SPI Memory Mapped Configuration Registers)
Memory Address:PBR[0]: SPIBAR + 60h
PBR[1]: SPIBAR + 64h
PBR[2]: SPIBAR + 68h
Attribute:
R/W
Default Value:00000000h
Size: 32 bits
Bit
Description
31
30:24
23:12
Write Protection Enable — R/W.
0 = Disable. The base and limit fields are ignored when this bit is cleared.
1 = Enable. The Base and Limit fields in this register are valid.
Reserved
Protected Range Limit — R/W. This field corresponds to SPI address bits 23:12 and
specifies the upper limit of the protected range.
11:0
NOTE: Any address greater than the value programmed in this field is unaffected by
this protected range.
Protected Range Base — R/W. This field corresponds to SPI address bits 23:12 and
specifies the lower base of the protected range.
NOTE: Address bits 11:0 are assumed to be 000h for the base comparison. Any
address less than the value programmed in this field is unaffected by this
protected range.
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15)
is set.
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Datasheet
671