82NM10 Datasheet, PDF (602/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
Bit
Description
13:0
Input Stream Payload Capability (INSTRMPAY) — RO. This field indicates the
maximum number of Words per frame for any single input stream. This measurement
is in 16-bit Word quantities per
48-kHz frame. The maximum supported is 24 Words (48B); therefore, a value of 18h is
reported in this register.
The value does not specify the number of words actually transmitted in the frame, but
is the size of the data as it will be placed into the controller's buffer (FIFO). Thus,
samples will be padded according to IPADTYPE before being stored into controller
buffer. To compute the supported streams, each sample is padded according to
IPADTYPE and then multiplied by the number of channels and samples per frame. If
this computed value is larger than INSTRMPAY, then that stream is not supported. As
the inbound stream tag is not stored with the samples it is not included in the word
count.
The value may be larger than INPAY register value in some cases, although values less
than INPAY may also be invalid due to overhead. Software must ensure that a format
that would cause more Words per frame than indicated is not programmed into the
Input Stream Descriptor Register.
18.2.12 INTCTL—Interrupt Control Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 20h
Attribute:
R/W
Default Value:
00000000hSize:32 bits
Bit
Description
31 Global Interrupt Enable (GIE) — R/W. Global bit to enable device interrupt
generation.
0 = Disable.
1 = Enable. The Intel HD Audio function is enabled to generate an interrupt. This
control is in addition to any bits in the bus specific address space, such as the
Interrupt Enable bit in the PCI configuration space.
NOTE: This bit is not affected by the D3_HOT to D0 transition.
30 Controller Interrupt Enable (CIE) — R/W. Enables the general interrupt for
controller functions.
0 = Disable.
1 = Enable. The controller generates an interrupt when the corresponding status bit
gets set due to a Response Interrupt, a Response Buffer Overrun, and State
Change events.
NOTE: This bit is not affected by the D3_HOT to D0 transition.
29:8 Reserved
602
Datasheet