82NM10 Datasheet, PDF (122/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.10.4
Note:
Front Side Bus Interrupt Delivery
For processors that support Front Side Bus (FSB) interrupt delivery, Chipset requires
that the I/O APIC deliver interrupt messages to the processor in a parallel manner,
rather than using the I/O APIC serial scheme.
This is done by Chipset writing (via DMI) to a memory location that is snooped by the
processor(s). The processor(s) snoop the cycle to know which interrupt goes active.
The following sequence is used:
1. When Chipset detects an interrupt event (active edge for edge-triggered mode or a
change for level-triggered mode), it sets or resets the internal IRR bit associated
with that interrupt.
2. Internally, Chipset requests to use the bus in a way that automatically flushes
upstream buffers. This can be internally implemented similar to a DMA device
request.
3. Chipset then delivers the message by performing a write cycle to the appropriate
address with the appropriate data. The address and data formats are described
below in Section 5.10.4.4.
FSB Interrupt Delivery compatibility with processor clock control depends on the
processor, not Chipset.
5.10.4.1
Edge-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on
the interrupt.
5.10.4.2
Level-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on
the interrupt. If after the EOI the interrupt is still active, then another “Assert Message”
is sent to indicate that the interrupt is still active.
5.10.4.3
Registers Associated with Front Side Bus Interrupt Delivery
Capabilities Indication: The capability to support Front Side Bus interrupt delivery is
indicated via ACPI configuration techniques. This involves the BIOS creating a data
structure that gets reported to the ACPI configuration software.
5.10.4.4
Interrupt Message Format
Chipset writes the message to PCI (and to the Host controller) as a 32-bit memory
write cycle. It uses the formats shown in Table 5-45 and Table 5-46 for the address and
data.
The local APIC (in the processor) has a delivery mode option to interpret Front Side Bus
messages as a SMI in which case the processor treats the incoming interrupt as a SMI
instead of as an interrupt. This does not mean that Chipset has any way to have a SMI
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