82NM10 Datasheet, PDF (495/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.1.43 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)
Address Offset: E0h–E3h
Default Value: 00000000h
Attribute:
Size:
R/W, R/WC
32 bits
Bits
31:12
11
Description
Reserved
BIST FIS Successful (BFS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = BIST FIS transmitted by Chipset received an R_OK completion status from the
device.
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
10 BIST FIS Failed (BFF) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = BIST FIS transmitted by Chipset received an R_ERR completion status from the
device.
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
9
Port 1 BIST FIS Initiate (P1BFI) — R/W. When a rising edge is detected on this bit
field, the Chipset initiates a BIST FIS to the device on Port 1, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will
only be initiated if a device on Port 1 is present and ready (not partial/slumber state).
After a BIST FIS is successfully completed, software must disable and re-enable the
port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to
return the Chipset to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P1BFI bit
to initiate another BIST FIS. This can be retried until the BIST FIS eventually
completes successfully
8
Port 0 BIST FIS Initiate (P0BFI) — R/W. When a rising edge is detected on this bit
field, the Chipset initiates a BIST FIS to the device on Port 0, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will
only be initiated if a device on Port 0 is present and ready (not partial/slumber state).
After a BIST FIS is successfully completed, software must disable and re-enable the
port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to
return the Chipset to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P0BFI bit
to initiate another BIST FIS. This can be retried until the BIST FIS eventually
completes successfully
7:2 BIST FIS Parameters. These 6 bits form the contents of the upper 6 bits of the BIST
FIS Pattern Definition in any BIST FIS transmitted by the Chipset. This field is not port
specific; its contents will be used for any BIST FIS initiated on port 0, port 1, port 2 or
port 3. The specific bit definitions are:
Bit 7: T – Far End Transmit mode
Bit 6: A – Align Bypass mode
Bit 5: S – Bypass Scrambling
Bit 4: L – Far End Retimed Loopback
Bit 3: F – Far End Analog Loopback
Bit 2: P – Primitive bit for use with Transmit mode
1:0 Reserved
Datasheet
495