82NM10 Datasheet, PDF (137/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
s
Table 5-55.System Power Plane
Plane
Controlled
By
Description
CPU
MAIN
MEMORY
DEVICE[n]
SLP_S3#
signal
SLP_S3#
signal
(S3_COLD)
or
SLP_S4#
signal
(S3_HOT)
SLP_S4#
signal
SLP_S5#
signal
GPIO
The SLP_S3# signal can be used to cut the power to the processor completely. For
Netbook systems, the DPRSLPVR support allows lowering the processor’s voltage
during the C4 state.
S3_HOT: The new S3_HOT state keeps more of the platform logic, including Chipset
core well, powered to reduce the cost of external power plane logic. SLP_S3# is
only used to remove power to the processor and to shut system clocks. This
impacts the board design, but there is no specific Chipset bit or strap needed to
indicate which option is selected.
S3_COLD: When SLP_S3# goes active, power can be shut off to any circuit not
required to wake the system from the S3 state. Since the S3 state requires that the
memory context be preserved, power must be retained to the main memory.
The processor, devices on the PCI bus, LPC I/F, and graphics will typically be shut
off when the Main power plane is shut, although there may be small subsections
powered.
S3_HOT: SLP_S4# is used to cut the main power well, rather than using SLP_S3#.
This impacts the board design, but there is no specific Chipset bit or strap needed
to indicate which option is selected.
When the SLP_S4# goes active, power can be shut off to any circuit not required to
wake the system from the S4. Since the memory context does not need to be
preserved in the S4 state, the power to the memory can also be shut down.
When SLP_S5# goes active, power can be shut to any circuit not required to wake
the system from the S5 state. Since the memory context does not need to be
preserved in the S5 state, the power to the memory can also be shut.
Individual subsystems may have their own power plane. For example, GPIO signals
may be used to control the power to disk drives, audio amplifiers, or the display
screen.
5.14.4
SMI#/SCI Generation
On any SMI# event taking place, Chipset asserts SMI# to the processor, which causes
it to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit
is set, SMI# goes inactive for a minimum of 4 PCICLK. If another SMI event occurs,
SMI# is driven active again.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or
23. The interrupt polarity changes depending on whether it is on an interrupt shareable
with a PIRQ or not (see Section 13.1.14). The interrupt remains asserted until all SCI
sources are removed.
Datasheet
137