82NM10 Datasheet, PDF (508/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.3.2.7
Bit
Description
22
21:8
7
6
5
4
3
2
1
0
PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and
PxIS.PRCS is set, the Chipset shall generate an interrupt.
Reserved - Should be written as 0
Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the Chipset
will generate an interrupt.
For systems that do not support an interlock switch, this bit shall be a read-only 0.
Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS
are set, the Chipset will generate an interrupt.
Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and
PxS.DPS are set, the Chipset will generate an interrupt
Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an
unknown FIS is received, the Chipset will generate this interrupt.
Set Device Bits FIS Interrupt Enable (SDBE) — R/W. When set, and GHC.IE and
PxS.SDBS are set, the Chipset will generate an interrupt.
DMA Setup FIS Interrupt Enable (DSE) — R/W. When set, and GHC.IE and PxS.DSS
are set, the Chipset will generate an interrupt.
PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PSS
are set, the Chipset will generate an interrupt.
Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set, and
GHC.IE and PxS.DHRS are set, the Chipset will generate an interrupt.
PxCMD—Port [1:0] Command Register (D31:F2)
Address Offset: Port 0: ABAR + 118h
Port 1: ABAR + 198h
Attribute:
R/W, RO, R/WO
Default Value: 0000w00wh
Size:
32 bits
where w = 00?0b (for?, see bit description)
508
Datasheet