82NM10 Datasheet, PDF (60/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
2.21 Power and Ground
Table 2-23.Power and Ground Signals
Name
Vcc3_3
Vcc1_05
Vcc1_5
V5REF
VccSus3_3
V5REF_Sus
VccRTC
Description
These pins provide the 3.3 V supply for core well I/O buffers (6pins). This
power may be shut off in S3, S4, S5 or G3 states.
These pins provide the 1.05 V supply for core well logic (4 pins). This power
may be shut off in S3, S4, S5 or G3 states.
These pins provide the 1.5 V supply for Logic and I/O (4 pins). This power may
be shut off in S3, S4, S5 or G3 states.
These pins provide the reference for 5 V tolerance on core well inputs (1 pins).
This power may be shut off in S3, S4, S5 or G3 states.
These pins provide the 3.3 V supply for resume well I/O buffers (4 pins). This
power is not expected to be shut off unless the system is unplugged in Nettop
configurations or the main battery is removed or completely drained and AC
power is not available in Netbook configurations.
This pin provides the reference for 5 V tolerance on resume well inputs (1 pin).
This power is not expected to be shut off unless the system is unplugged in
Nettop configurations or the main battery is removed or completely drained
and AC power is not available in Netbook configurations.
This pin provides the 3.3 V (can drop to 2.0 V min. in G3 state) supply for the
RTC well (1 pin). This power is not expected to be shut off unless the RTC
battery is removed or completely drained.
VccUSBPLL
VccDMIPLL
VccSATAPLL
V_CPU_IO
Vss
NOTE: Implementations should not attempt to clear CMOS by using a jumper
to pull VccRTC low. Clearing CMOS in a chipset-based platform can be
done by using a jumper on RTCRST# or GPI.
This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must
be powered even if USB not used.
This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states.
This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must
be powered even if SATA not used.
These pins are powered by the same supply as the processor I/O voltage (1
pins). This supply is used to drive the processor interface signals listed in
Table 2-14.
Grounds (59 pins).
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Datasheet