82NM10 Datasheet, PDF (144/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
If an internal source requests the clock to be re-started, Chipset re-asserts CLKRUN#,
and simultaneously deasserts the STP_PCI# signal.
5.14.6.5
LPC Devices and CLKRUN# (Netbook Only)
If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA
(Netbook Only) or LPC serial interrupt, then it can assert CLKRUN#. Note that LPC
devices running DMA or bus master cycles will not need to assert CLKRUN#, since
Chipset asserts it on their behalf.
The LDRQ# inputs are ignored by Chipset when the PCI clock is stopped to the LPC
devices in order to avoid misinterpreting the request. Chipset assumes that only one
more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#.
Upon deassertion of STP_PCI#, Chipset assumes that the LPC device receives its first
clock rising edge corresponding to chipset’s second PCI clock rising edge after the
deassertion.
5.14.7
5.14.7.1
5.14.7.2
Sleep States
Sleep State Overview
Chipset directly supports different sleep states (S1–S5) that are entered by setting the
SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based on
several assumptions:
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because
the processor can only perform one register access at a time. A request to Sleep
has higher priority than throttling.
• Prior to setting the SLP_EN bit, the software turns off processor-controlled
throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN
bit disables thermal throttling (since S1–S5 sleep state has higher priority).
• The G3 state cannot be entered via any software mechanism. The G3 state
indicates a complete loss of power.
Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• Masking interrupts, turning off all bus master enable bits, setting the desired type
in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts
to gracefully put the system into the corresponding Sleep state.
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button
Override event. In this case the transition to the S5 state is less graceful, since
there are no dependencies on observing Stop-Grant cycles from the processor or
on clocks other than the RTC clock.
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Datasheet