82NM10 Datasheet, PDF (315/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
Bit
Description
2:0 Receive Unit Command (RUC) — R/W. Valid values are:
000 = NOP: Does not affect the current state of the unit.
001 = RU Start: Enables the receive unit. The pointer to the RFA must be placed in the
SCB General POinter before using this command. The device pre-fetches the
first RFD and the first RBD (if in flexible mode) in preparation to receive
incoming frames that pass its address filtering.
010 = RU Resume: Resume frame reception (only when in suspended state).
011 = RCV DMA Redirect: Resume the RCV DMA when configured to “Direct DMA
Mode.” The buffers are indicated by an RBD chain which is pointed to by an
offset stored in the General Pointer Register (this offset will be added to the RU
Base).
100 = RU Abort: Abort RU receive operation immediately.
101 = Load Header Data Size (HDS): This value defines the size of the Header
portion of the RFDs or Receive buffers. The HDS value is defined by the lower
14 bits of the SCB General Pointer, so bits 31:15 should always be set to 0’s
when using this command. Once a Load HDS command is issued, the device
expects only to find Header RFDs, or be used in “RCV Direct DMA mode” until it
is reset. Note that the value of HDS should be an even, non-zero number.
110 = Load RU Base: The device’s internal RU Base Register is loaded with the value
in the SCB General Pointer.
111 = RBD Resume: Resume frame reception into the RFA. This command should
only be used when the RU is already in the “No Resources due to no RBDs”
state or the “Suspended with no more RBDs” state.
11.2.3
SCB_GENPNT—System Control Block General Pointer
Register (LAN Controller—B1:D8:F0)
Offset Address: 04h–07h
Default Value: 0000 0000h
Attribute:
Size:
R/W
32 bits
Bit
Description
15:0
SCB General Pointer — R/W. The SCB General Pointer register is programmed by
software to point to various data structures in main memory depending on the current
SCB Command word.
11.2.4
PORT—PORT Interface Register
(LAN Controller—B1:D8:F0)
Offset Address: 08h–0Bh
Default Value: 0000 0000h
Attribute:
Size:
R/W (special)
32 bits
The PORT interface allows the processor to reset the chipset’s internal LAN controller, or
perform an internal self test. The PORT DWord may be written as a 32-bit entity, two
16-bit entities, or four
8-bit entities. The LAN controller will only accept the command after the high byte
(offset 0Bh) is written; therefore, the high byte must be written last.
Datasheet
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