82NM10 Datasheet, PDF (428/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
6
TCOSCI_EN — R/W.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
5
AC97_EN — R/W.
0 = Disable.
1 = Enables the setting of the AC97_STS to generate a wake event.
NOTE: This bit is also used for Intel HD Audio when the Intel High Definition Audio
host controller is enabled.
4
USB2_EN — R/W.
0 = Disable.
1 = Enables the setting of the USB2_STS to generate a wake event.
3
USB1_EN — R/W.
0 = Disable.
1 = Enables the setting of the USB1_STS to generate a wake event.
2
SWGPE_EN— R/W. This bit allows software to control the assertion of SWGPE_STS
bit. This bit This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is
written to a 1, hardware will set SWGPE_STS (acts as a level input)
If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1s, an SCI will be generated
If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1, then an
SMI# will be generated
1
HOT_PLUG_EN — R/W.
0 = Disables SCI generation upon the HOT_PLUG_STS bit being set.
1 = Enables the Chipset to cause an SCI when the HOT_PLUG_STS bit is set. This is
used to allow the PCI Express ports to cause an SCI due to hot-plug events.
1
Reserved
0
THRM_EN — R/W.
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set
the THRM_STS bit and generate a power management event (SCI or SMI).
13.8.3.12 SMI_EN—SMI Control and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 30h
00000000h
No
Core
Attribute:
Size:
Usage:
Note:
This register is symmetrical to the SMI status register.
R/W, R/W (special), WO
32 bit
ACPI or Legacy
Bit
31:26
25
24:19
18
Description
Reserved
Reserved
Reserved
INTEL_USB2_EN — R/W.
0 = Disable
1 = Enables Intel-Specific USB2 SMI logic to cause SMI#.
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Datasheet