82NM10 Datasheet, PDF (648/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.49 VCAP2—Virtual Channel Capability 2 Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 108h–10Bh
Default Value: 00000001h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24 VC Arbitration Table Offset (ATO) — RO. This field indicates that no table is present
for VC arbitration since it is fixed.
23:0 Reserved.
19.1.50 PVC—Port Virtual Channel Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 10Ch–10Dh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:4
3:1
0
Reserved.
VC Arbitration Select (AS) — R/W. This field indicates which VC should be
programmed in the VC arbitration table. The root port takes no action on the setting of
this field since there is no arbitration table.
Load VC Arbitration Table (LAT) — R/W. This bit indicates that the table
programmed should be loaded into the VC arbitration table. This bit always returns 0
when read.
19.1.51 PVS — Port Virtual Channel Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 10Eh–10Fh
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:1
0
Reserved.
VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of
the VC Arbitration table when it is being updated. This field is always 0 in the root port
since there is no VC arbitration table.
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Datasheet