82NM10 Datasheet, PDF (635/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
Bit
Description
11:10 Active State Link PM Support (APMS) — R/WO. This field indicates what level of
active state link power management is supported on the root port.
Bits
00b
01b
10b
11b
Definition
Neither L0s nor L1 are supported
L0s Entry Supported
L1 Entry Supported
Both L0s and L1 Entry Supported
9:4 Maximum Link Width (MLW) — RO. For the root ports, several values can be taken,
based upon the value of the chipset configuration register field RPC.PC1 (Chipset
Configuration Registers:Offset 0224h:bits1:0) for Ports 1–4.
Port #
1
2
3
4
RPC.PC1=00b
01h
01h
01h
01h
RPC.PC1=11b
04h
01h
01h
01h
3:0 Maximum Link Speed (MLS) — RO. Set to 1h to indicate the link speed is 2.5 Gb/s.
19.1.28 LCTL—Link Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 50h-51h
Default Value: 0000h
Attribute:
Size:
R/W, WO, RO
16 bits
Bit
Description
15:8
7
6
5
Reserved
Extended Synch (ES) — R/W.
0 = Extended synch disabled.
1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from
L1 prior to entering L0.
Common Clock Configuration (CCC) — R/W.
0 = The Chipset and device are not using a common reference clock.
1 = The Chipset and device are operating with a distributed common reference clock.
Retrain Link (RL) — WO.
0 = This bit always returns 0 when read.
1 = The root port will train its downstream link.
NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5:52, bit 11) to check the status
of training.
4 Link Disable (LD) — R/W.
0 = Link enabled.
1 = The root port will disable the link.
3 Read Completion Boundary Control (RCBC) — RO. This bit indicates that the read
completion boundary is 64 bytes.
2 Reserved
Datasheet
635