82NM10 Datasheet, PDF (452/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

UHCI Controllers Registers
Bit
Description
4 Capabilities List — RO. Hardwired to 0.
3 Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the
input of the enable/disable logic.
0 = Interrupt is de-asserted.
1 = Interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
2:0 Reserved
14.1.5
14.1.6
14.1.7
RID—Revision Identification Register
(USB—D29:F0/F1/F2/F3)
Offset Address: 08h
Default Value: See bit description
Bit
7:0 Revision ID — RO.
Attribute:
Size:
Description
RO
8 bits
PI—Programming Interface Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
09hAttribute:RO
Default Value:
00hSize:8 bits
Bit
Description
7:0 Programming Interface — RO.
00h = No specific register level programming interface defined.
SCC—Sub Class Code Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
0AhAttribute:RO
Default Value:
03hSize:8 bits
Bit
Description
7:0 Sub Class Code (SCC) — RO.
03h = USB host controller.
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Datasheet