82NM10 Datasheet, PDF (476/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.1.12 SCMD_BAR—Secondary Command Block Base Address
Register (IDE D31:F1)
Address Offset: 18h–1Bh
Default Value: 00000001h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:16 Reserved
15:3 Base Address — R/W. This field provides the base address of the I/O space (8
consecutive I/O locations).
2:1 Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command
Block.
15.1.13 SCNL_BAR—Secondary Control Block Base Address
Register (IDE D31:F1)
Address Offset: 1Ch–1Fh
Default Value: 00000001h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:16 Reserved
15:2 Base Address — R/W. This field provides the base address of the I/O space (4
consecutive I/O locations).
1 Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command
Block.
15.1.14 BAR — Legacy Bus Master Base Address Register
(SATA–D31:F2)
Address Offset: 20h–23h
Default Value: 00000001h
Attribute:
Size:
R/W, RO
32 bits
The Bus Master IDE interface function uses Base Address register 5 to request a 16-
byte IO space to provide a software interface to the Bus Master functions. Only 12
bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]
are used to decode the address.
Bit
Description
31:16 Reserved
15:4 Base Address — R/W. This field provides the base address of the I/O space (16
consecutive I/O locations).
3:1 Reserved
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