82NM10 Datasheet, PDF (131/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0
• The A20GATE input signal is a 0
The A20GATE input signal is expected to be generated by the external microcontroller
(KBC).
5.13.1.2
Note:
INIT# (Initialization)
The INIT# signal is active (driven low) based on any one of several events described in
Table 5-50. When any of these events occur, INIT# is driven low for 16 PCI clocks, then
driven high.
The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if
INIT# is supposed to go active while STPCLK# is asserted, it actually goes active after
STPCLK# goes inactive.
This section refers to INIT#, but applies to two signals: INIT# and INIT3_3V#, as
INIT3_3V# is functionally identical to INIT#, but signaling at 3.3 V.
Table 5-50.INIT# Going Active
Cause of INIT# Going Active
Comment
Shutdown special cycle from processor.
PORT92 write, where INIT_NOW (bit 0) transitions
from a 0 to a 1.
PORTCF9 write, where SYS_RST (bit 1) was a 0
and RST_CPU (bit 2) transitions from 0 to 1.
RCIN# input signal goes low. RCIN# is expected
to be driven by the external microcontroller
(KBC).
CPU BIST
0 to 1 transition on RCIN# must occur
before Chipset will arm INIT# to be
generated again.
NOTE: RCIN# signal is expected to be high
during S3_HOT and low during
S3_COLD, S4, and S5 states.
Transition on the RCIN# signal in
those states (or the transition to
those states) may not necessarily
cause the INIT# signal to be
generated to the processor.
To enter BIST, software sets CPU_BIST_EN
bit and then does a full processor reset
using the CF9 register.
5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric Error)
Chipset supports the coprocessor error function with the FERR#/IGNNE# pins. The
function is enabled via the COPROC_ERR_EN bit (Chipset Config Registers:Offset
31FFh:bit 1). FERR# is tied directly to the Coprocessor Error signal of the processor. If
FERR# is driven active by the processor, IRQ13 goes active (internally). When it
detects a write to the COPROC_ERR register (I/O Register F0h), Chipset negates the
internal IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driven
inactive. IGNNE# is not driven active unless FERR# is active.
Datasheet
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