82NM10 Datasheet, PDF (26/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

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Other Clocks ..........................................................................................57
Miscellaneous Signals ..............................................................................57
Intel HD Audio Link Signals ......................................................................58
Serial Peripheral Interface (SPI) Signals.....................................................59
General Purpose I/O Signals.....................................................................59
Power and Ground Signals .......................................................................60
Functional Strap Definitions......................................................................61
Integrated Pull-Up and Pull-Down Resistors ................................................65
Power Plane and States for Output and I/O Signals .....................................67
Power Plane for Input Signals ...................................................................71
Chipset and System Clock Domains...........................................................74
PCI Bridge Initiator Cycle Types................................................................76
Type 1 Address Format............................................................................79
MSI vs. PCI IRQ Actions...........................................................................81
Advanced TCO Functionality .....................................................................93
LPC Cycle Types Supported ......................................................................99
Start Field Bit Definitions .........................................................................99
Cycle Type Bit Definitions ...................................................................... 100
Transfer Size Bit Definition..................................................................... 100
SYNC Bit Definition ............................................................................... 101
DMA Transfer Size ................................................................................ 106
Address Shifting in 16-Bit I/O DMA Transfers............................................ 106
Counter Operating Modes ...................................................................... 112
Interrupt Controller Core Connections...................................................... 115
Interrupt Status Registers...................................................................... 116
Content of Interrupt Vector Byte ............................................................. 116
APIC Interrupt Mapping ......................................................................... 123
Interrupt Message Address Format.......................................................... 125
Interrupt Message Data Format .............................................................. 125
Stop Frame Explanation......................................................................... 127
Data Frame Format............................................................................... 128
Configuration Bits Reset by RTCRST# Assertion ........................................ 131
INIT# Going Active ............................................................................... 133
NMI Sources ........................................................................................ 135
DP Signal Differences ............................................................................ 135
General Power States for Systems Using Chipset....................................... 137
State Transition Rules for Chipset ........................................................... 138
System Power Plane.............................................................................. 139
Causes of SMI# and SCI ........................................................................ 140
Break Events (Netbook)......................................................................... 144
Sleep Types ......................................................................................... 148
Causes of Wake Events.......................................................................... 148
GPI Wake Events .................................................................................. 149
Transitions Due to Power Failure ............................................................. 150
Transitions Due to Power Button ............................................................. 152
Transitions Due to RI# Signal................................................................. 153
Write Only Registers with Read Paths in ALT Access Mode .......................... 156
PIC Reserved Bits Return Values ............................................................. 158
Register Write Accesses in ALT Access Mode ............................................. 158
Chipset Clock Inputs ............................................................................. 161
Heartbeat Message Data ........................................................................ 168
SATA Features Support in Chipset ........................................................... 169
SATA Feature Description ...................................................................... 169
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Datasheet