82NM10 Datasheet, PDF (499/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.2.3
BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2)
Address Offset: Primary: BAR + 04h–07h Attribute:
Secondary: BAR + 0Ch–0Fh
Default Value: All bits undefined
Size:
R/W
32 bits
Bit
Description
31:2
1:0
Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to
A[31:2]. The Descriptor Table must be DWord-aligned. The Descriptor Table must not
cross a 64-K boundary in memory.
Reserved
15.3 AHCI Registers (D31:F2)
Note:
These registers are AHCI-specific and available only on Chipset components that
support AHCI (not on the 82801GB Chipset) and when the Chipset is properly
configured. The Serial ATA Status, Control, and Error registers are special exceptions
and may be accessed on all Chipset components if properly configured (see section
Section 15.1.35 for details).
The memory mapped registers within the SATA controller exist in non-cacheable
memory space. Additionally, locked accesses are not supported. If software attempts to
perform locked transactions to the registers, indeterminate results may occur. Register
accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte
alignment boundary.
The registers are divided into two sections – generic host control and port control. The
port control registers are the same for all ports, and there are as many registers banks
as there are ports.
Table 15-137.AHCI Register Address Map
ABAR + Mnemon
Offset
ic
Register
00–1Fh
20h–FFh
100h–17Fh
180h–1FFh
200h–3FFh
GHC
—
P0PCR
P1PCR
—
Generic Host Control
Reserved
Port 0 port control registers
Port 1 port control registers
Reserved
Datasheet
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