82NM10 Datasheet, PDF (174/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
If a timer has been configured to level-triggered mode, then its interrupt must be
cleared by the software. This is done by reading the interrupt status register and
writing a 1 back to the bit position for the interrupt to be cleared.
Independent of the mode, software can read the value in the main counter to see how
time has passed between when the interrupt was generated and when it was first
serviced.
If Timer 0 is set up to generate a periodic interrupt, the software can check to see how
much time remains until the next interrupt by checking the timer value register.
5.17.7
Issues Related to 64-Bit Timers with 32-Bit Processors
A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit
instructions. However, a 32-bit processor may not be able to directly read 64-bit timer.
A race condition comes up if a 32-bit processor reads the 64-bit register using two
separate 32-bit reads. The danger is that just after reading one half, the other half rolls
over and changes the first half.
If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before
reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not
want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the
TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper
32-bits are always 0.
5.18
USB UHCI Host Controllers (D29:F0, F1, F2, and
F3)
Chipset contains four USB 2.0 full/low-speed host controllers that support the standard
Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host Controller
(UHC) includes a root hub with two separate USB ports each, for a total of eight USB
ports.
• Overcurrent detection on all eight USB ports is supported. The overcurrent inputs
are not 5 V tolerant, and can be used as GPIs if not needed.
• Chipset’s UHCI host controllers are arbitrated differently than standard PCI devices
to improve arbitration latency.
• The UHCI controllers use the Analog Front End (AFE) embedded cell that allows
support for USB full-speed signaling rates, instead of USB I/O buffers.
5.18.1
Data Structures in Main Memory
Section 3.1 - 3.3 of the Universal Host Controller Interface Specification, Revision 1.1
details the data structures used to communicate control, status, and data between
software and Chipset.
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Datasheet