82NM10 Datasheet, PDF (425/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
10
BATLOW_STS — R/WC. (Netbook Only) Software clears this bit by writing a 1 to it.
(Netbook _{0 = BATLOW# Not asserted}
Only) _{1 = Set by hardware when the BATLOW# signal is asserted.}
9
PCI_EXP_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware to indicate that:
• The PME event message was received on one or more of the PCI Express* ports
• An Assert PMEGPE message received from the (G)MCH/CPU via DMI
NOTES:
1.
The PCI WAKE# pin has no impact on this bit.
2.
If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then
a Deassert PMEGPE message must be received prior to the software write in
order for the bit to be cleared.
3.
If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the
level-triggered SCI will remain active.
4.
A race condition exists where the PCI Express device sends another PME
message because the PCI Express device was not serviced within the time
when it must resend the message. This may result in a spurious interrupt,
and this is comprehended and approved by the PCI Express* Specification,
Revision 1.0a. The window for this race condition is approximately
95–105 milliseconds.
8
RI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RI# input signal goes active.
7
SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can
independently cause an SMI# or SCI, so this bit does not need to do so (unlike the
other bits in this register). Software clears this bit by writing a 1 to it.
0 = Wake event Not caused by the chipset’s SMBus logic.
1 = Set by hardware to indicate that the wake event was caused by the chipset’s
SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the
system is already awake. The SMI handler should then clear this bit.
NOTES:
1.
This bit is set by the SMBus slave command 01h (Wake/SMI#) even when
the system is in the S0 state. Therefore, to avoid an instant wake on
subsequent transitions to sleep states, software must clear this bit after each
reception of the Wake/SMI# command or just prior to entering the sleep
state.
2.
If SMB_WAK_STS is set due to SMBus slave receiving a message, it will be
cleared by internal logic when a THRMTRIP# event happens or a Power
Button Override event. However, THRMTRIP# or Power Button Override
event will not clear SMB_WAK_STS if it is set due to SMBALERT# signal
going active.
3.
The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by
software before the SMB_WAK_STS bit is cleared.
6
TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = TOC logic did Not cause SCI.
1 = Set by hardware when the TCO logic causes an SCI.
Datasheet
425