82NM10 Datasheet, PDF (558/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
17.1.10 SVID — Subsystem Vendor Identification Register
(SMBUS—D31:F2/F4)
Address Offset: 2Ch–2Dh
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
15:0
Subsystem Vendor ID (SVID) — RO. The SVID register, in combination with the
Subsystem ID (SID) register, enables the operating system (OS) to distinguish
subsystems from each other. The value returned by reads to this register is the same
as that which was written by BIOS into the IDE SVID register.
NOTE: Software can write to this register only once per core well reset. Writes should
be done as a single 16-bit cycle.
17.1.11 SID — Subsystem Identification Register
(SMBUS—D31:F2/F4)
Address Offset: 2Eh–2Fh
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
Bit
Description
15:0
Subsystem ID (SID) — RO. The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems from each other. The
value returned by reads to this register is the same as that which was written by BIOS
into the IDE SID register.
NOTE: Software can write to this register only once per core well reset. Writes should
be done as a single 16-bit cycle.
17.1.12 INT_LN—Interrupt Line Register (SMBUS—D31:F3)
Address Offset: 3Ch
Default Value: 00h
Attributes:
Size:
R/W
8 bits
Bit
Description
7:0 Interrupt Line (INT_LN) — R/W. This data is not used by the Chipset. It is to
communicate to software the interrupt line that the interrupt pin is connected to
PIRQB#.
17.1.13 INT_PN—Interrupt Pin Register (SMBUS—D31:F3)
Address Offset: 3Dh
Default Value: See description
Attributes:
Size:
RO
8 bits
Bit
Description
7:0 Interrupt PIN (INT_PN) — RO. This reflects the value of D31IP.SMIP in chipset
configuration space.
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