82NM10 Datasheet, PDF (613/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
Bit
23:20
19
18
17:16
15:5
4
3
2
1
Description
Stream Number — R/W. This value reflects the Tag associated with the data
being transferred on the link.
When data controlled by this descriptor is sent out over the link, it will have its
stream number encoded on the SYNC signal.
When an input stream is detected on any of the SDI signals that match this value,
the data samples are loaded into FIFO associated with this descriptor.
Note that while a single SDI input may contain data from more than one stream
number, two different SDI inputs may not be configured with the same stream
number.
0000 = Reserved
0001 = Stream 1
........
1110 = Stream 14
1111 = Stream 15
Bidirectional Direction Control — RO. This bit is only meaningful for
bidirectional streams; therefore, this bit is hardwired to 0.
Traffic Priority — RO. Hardwired to 1 indicating that all streams will use VC1 if it
is enabled through the PCI Express* registers.
Stripe Control — RO. This bit is only meaningful for input streams; therefore, this
bit is hardwired to 0.
Reserved
Descriptor Error Interrupt Enable — R/W.
0 = Disable
1 = An interrupt is generated when the Descriptor Error Status bit is set.
FIFO Error Interrupt Enable — R/W.
0 = Disable.
1 = Enable. This bit controls whether the occurrence of a FIFO error (overrun for
input or underrun for output) will cause an interrupt or not. If this bit is not
set, bit 3 in the Status register will be set, but the interrupt will not occur.
Either way, the samples will be dropped.
Interrupt on Completion Enable — R/W.
0 = Disable.
1 = Enable. This bit controls whether or not an interrupt occurs when a buffer
completes with the IOC bit set in its descriptor. If this bit is not set, bit 2 in the
Status register will be set, but the interrupt will not occur.
Stream Run (RUN) — R/W.
0 = Disable. The DMA engine associated with this input stream will be disabled.
The hardware will report a 0 in this bit when the DMA engine is actually
stopped. Software must read a 0 from this bit before modifying related control
registers or restarting the DMA engine.
1 = Enable. The DMA engine associated with this input stream will be enabled to
transfer data from the FIFO to the main memory. The SSYNC bit must also be
cleared in order for the DMA engine to run. For output streams, the cadence
generator is reset whenever the RUN bit is set.
Datasheet
613