82NM10 Datasheet, PDF (318/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
Bit
Description
27:26
Opcode — R/W (special). These bits define the opcode:
00 = Reserved
01 = MDI write
10 = MDI read
11 = Reserved
25:21 LAN Connect Address — R/W (special). This field of bits contains the LAN Connect
address.
20:16 LAN Connect Register Address — R/W (special). This field contains the LAN Connect
Register Address.
15:0
Data — R/W (special). In a write command, software places the data bits in this field,
and the LAN controller transfers the data to the external LAN Connect component.
During a read command, the LAN controller reads these bits serially from the LAN
Connect, and software reads the data from this location.
11.2.7
11.2.8
Note:
REC_DMA_BC—Receive DMA Byte Count Register
(LAN Controller—B1:D8:F0)
Offset Address: 14h–17h
Default Value: 0000 0000h
Attribute:
Size:
RO
32 bits
Bit
Description
31:0 Receive DMA Byte Count — RO. This field keeps track of how many bytes of receive
data have been passed into host memory via DMA.
EREC_INTR—Early Receive Interrupt Register
(LAN Controller—B1:D8:F0)
Offset Address: 18h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
The Early Receive Interrupt register allows the internal LAN controller to generate an
early interrupt depending on the length of the frame. The LAN controller will generate
an interrupt at the end of the frame regardless of whether or not Early Receive
Interrupts are enabled.
It is recommended that software not use this register unless receive interrupt latency
is a critical performance issue in that particular software environment. Using this
feature may reduce receive interrupt latency, but will also result in the generation of
more interrupts, which can degrade system efficiency and performance in some
environments.
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Datasheet