82NM10 Datasheet, PDF (512/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Bit
Description
31:16 Reserved
15:8 Error (ERR) — RO. Contains the latest copy of the task file error register.
7:0 Status (STS) — RO. Contains the latest copy of the task file status register. Fields of
note in this register that affect AHCI.
Bit
Field
Definition
7
BSY
Indicates the interface is busy
6:4
N/A
Not applicable
3
DRQ
Indicates a data transfer is requested
2:1
N/A
Not applicable
0
ERR
Indicates an error during the transfer
15.3.2.9
PxSIG—Port [1:0] Signature Register (D31:F2)
Address Offset: Port 0: ABAR + 124h
Attribute:
RO
Port 1: ABAR + 1A4h
Default Value: FFFFFFFFh
Size:
32 bits
This is a 32-bit register which contains the initial signature of an attached device when
the first D2H Register FIS is received from that device. It is updated once after a reset
sequence.
Bit
Description
31:0 Signature (SIG) — RO. Contains the signature received from a device on the first D2H
register FIS. The bit order is as follows:
Bit
31:24
23:16
15:8
7:0
Field
LBA High Register
LBA Mid Register
LBA Low Register
Sector Count Register
15.3.2.10 PxSSTS—Port [1:0] Serial ATA Status Register (D31:F2)
Address Offset: Port 0: ABAR + 128h
Attribute:
RO
Port 1: ABAR + 1A8h
Default Value: 00000000h
Size:
32 bits
This is a 32-bit register that conveys the current state of the interface and host. The
Chipset updates it continuously and asynchronously. When the Chipset transmits a
COMRESET to the device, this register is updated to its reset values.
Bit
31:12 Reserved
Description
512
Datasheet