82NM10 Datasheet, PDF (665/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Serial Peripheral Interface (SPI)
Table 21-150.Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers) (Sheet 2 of 2)
SPIBAR +
Offset
38h–3Fh
Mnemonic
SPID6
Register Name
SPI Data 6
40h–47h
SPID7
SPI Data 7
50h–53h
54h–55h
56h–57h
58h–5Fh
BBAR
PREOP
OPTYPE
OPMENU
BIOS Base Address Configuration
Prefix Opcode Configuration
Opcode Type Configuration
Opcode Menu Configuration
60h–63h
64h–67h
68h–6Bh
6Ch–6Fh
PBR0
PBR1
PBR2
—
Protected BIOS Range 0
Protected BIOS Range 1
Protected BIOS Range 2
Reserved
Default
00000000
00000000h
00000000
00000000h
00000000h
0004h
0000h
00000000
00000005h
00000000h
00000000h
00000000h
—
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
21.1.1
SPIS—SPI Status Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 00h
Default Value:
Attribute:
RO, R/WC, R/WLO
See bit descriptionSize:16 bits
Bit
15
14:4
3
Description
SPI Configuration Lock-Down — R/WLO.
0 = No Lock-Down (Default)
1 = SPI Static Configuration information in offsets 50h through 6Fh can not be
overwritten. Once set to 1, this bit can only be cleared by a hardware reset.
Reserved
Blocked Access Status — R/WC.
0 = Not blocked (Default)
1 = Hardware sets this bit to 1 when an access is blocked from running on the SPI
interface due to one of the protection policies or when any of the programmed cycle
registers is written while a programmed access is already in progress. This bit is set
for both programmed accesses and direct memory reads that get blocked.
NOTE: This bit remains asserted until cleared by software writing a 1 or hardware
reset.
2 Cycle Done Status— R/WC.
0 = Not done (Default)
1 = The Chipset sets this bit to 1 when the SPI Cycle completes (i.e., SCIP bit is 0) after
software sets the SCGO bit.
NOTE: This bit remains asserted until cleared by software writing a 1 or hardware
reset.
NOTE: Software must make sure this bit is cleared prior to enabling the SPI SMI#
assertion for a new programmed access.
NOTE: This bit gets set after the Status Register Polling sequence completes after reset
deasserts. It is cleared before and during that sequence.
Datasheet
665