82NM10 Datasheet, PDF (102/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Figure 5-9. LPC Bridge SERR# Generation
PCISTS.DPE
(D31:F0:06h, bit15)
PCISTS.DPED
(D31:F0:06h, bit 8)
LPC Error Sync
Received
PCICMD.SERR_EN
(D31:F0:04h, bit 8)
PCISTS.SSE
(D31:F0:06h, bit 14)
SERR#
5.6
DMA Operation (D31:F0)
Chipset supports LPC DMA using chipset’s DMA controller. The DMA controller has
registers that are fixed in the lower 64 KB of I/O space. The DMA controller is
configured using registers in the PCI configuration space. These registers allow
configuration of the channels for use by LPC DMA.
The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with
seven independently programmable channels (Figure 5-10). DMA controller 1 (DMA-1)
corresponds to DMA channels 0–3 and DMA controller 2 (DMA-2) corresponds to
channels 5–7. DMA channel 4 is used to cascade the two controllers and defaults to
cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for
any other purpose. In addition to accepting requests from DMA slaves, the DMA
controller also responds to requests that software initiates. Software may initiate a
DMA service request by setting any bit in the DMA Channel Request Register to a 1.
Figure 5-10. Chipset DMA Controller
Channel 0
Channel 1
Channel 2
Channel 3
DMA-1
Channel 4
Channel 5
Channel 6
Channel 7
DMA-2
Each DMA channel is hardwired to the compatible settings for DMA device size:
channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are
hardwired to 16-bit, count-by-words (address shifted) transfers.
Chipset provides 24-bit addressing in compliance with the ISA-Compatible
specification. Each channel includes a 16-bit ISA-Compatible Current Register which
holds the 16 least-significant bits of the 24-bit address, an ISA-Compatible Page
Register which contains the eight next most significant bits of address.
The DMA controller also features refresh address generation, and autoinitialization
following a DMA termination.
102
Datasheet