82NM10 Datasheet, PDF (125/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 frames
indicates that an active-high ISA interrupt is not being requested, but a low level
during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low
interrupt is being requested.
• Recovery Phase. During this phase, the device drives the SERIRQ line high if in
the Sample Phase it was driven low. If it was not driven in the sample phase, it is
tri-stated in this phase.
• Turn-around Phase. The device tri-states the SERIRQ line
5.11.3
Stop Frame
After all data frames, a Stop Frame is driven by Chipset. The SERIRQ signal is driven
low by Chipset for 2 or 3 PCI clocks. The number of clocks is determined by the SERIRQ
configuration register. The number of clocks determines the next mode:
Table 5-47.Stop Frame Explanation
Stop Frame Width
Next Mode
2 PCI clocks
3 PCI clocks
Quiet Mode. Any SERIRQ device may initiate a Start Frame
Continuous Mode. Only the host may initiate a Start Frame
5.11.4
Specific Interrupts Not Supported via SERIRQ
There are three interrupts seen through the serial stream that are not supported by
Chipset. These interrupts are generated internally, and are not sharable with other
devices within the system. These interrupts are:
• IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.
• IRQ8#. RTC interrupt can only be generated internally.
• IRQ13. Floating point error interrupt generated off of the processor assertion of
FERR#.
Chipset ignores the state of these interrupts in the serial stream, and does not adjust
their level based on the level seen in the serial stream.
5.11.5
Data Frame Format
Table 5-48 shows the format of the data frames. For the PCI interrupts (A–D), the
output from Chipset is ANDed with the PCI input signal. This way, the interrupt can be
signaled via both the PCI interrupt input signal and via the SERIRQ signal (they are
shared).
Datasheet
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