82NM10 Datasheet, PDF (157/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
3. If a design has an active-low reset button electrically AND’d with the PWROK signal
from the power supply and the processor’s voltage regulator module Chipset
PWROK_FLR bit will be set. Chipset treats this internally as if the RSMRST# signal
had gone active. However, it is not treated as a full power failure. If PWROK goes
inactive and then active (but RSMRST# stays high), then Chipset reboots
(regardless of the state of the AFTERG3 bit). If the RSMRST# signal also goes low
before PWROK goes high, then this is a full power failure, and the reboot policy is
controlled by the AFTERG3 bit.
4. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that
are less than one RTC clock period may not be detected by Chipset.
5. In the case of true PWROK failure, PWROK goes low first before the VRMPWRGD.
5.14.11.4 CPUPWRGD Signal
This signal is connected to the processor’s VRM via the VRMPWRGD signal and is
internally AND’d with the PWROK signal that comes from the system power supply.
5.14.11.5 VRMPWRGD Signal
VRMPWRGD is an input from the regulator indicating that all of the outputs from the
regulator are on and within specification. VRMPWRGD may go active before or after the
PWROK from the main power supply. Chipset has no dependency on the order in which
these two signals go active or inactive.
5.14.11.6 BATLOW# (Battery Low) (Netbook Only)
The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not
sufficient power. It also causes an SMI# if the system is already in an S0 state.
5.14.11.7 Controlling Leakage and Power Consumption
during Low-Power States
To control leakage in the system, various signals tri-state or go low during some low-
power states.
General principles:
• All signals going to powered down planes (either internally or externally) must be
either tri-stated or driven low.
• Signals with pull-up resistors should not be low during low-power states. This is to
avoid the power consumed in the pull-up resistor.
• Buses should be halted (and held) in a known state to avoid a floating input
(perhaps to some other device). Floating inputs can cause extra power
consumption.
Based on the above principles, the following measures are taken:
• During S3 (STR), all signals attached to powered down planes are tri-stated or
driven low.
Datasheet
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