82NM10 Datasheet, PDF (80/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.2
PCI Express* Root Ports (D28:F0,F1,F2,F3)
There are four root ports available in Chipset. These all reside in device 28, and take
function 0 – 3. Port 1 is function 0, port 2 is function 1, port 3 is function 2, port 4 is
function 3.
Optionally, PCI Express ports 1-4 can be configured as a single one x4 port identified as
port 1. This is accomplished by placing external pull-up resistors on HDA_SDOUT and
HDA_SYNC. When these signals are sampled high on PWROK assertion, this will be
registered in the Port Configuration field of the Root Port Configuration Register and the
corresponding ports will be configured as one x4 port.
5.2.1
Interrupt Generation
The root port generates interrupts on behalf of Hot-Plug and power management
events, when enabled. These interrupts can either be pin based, or can be MSIs, when
enabled.
When an interrupt is generated via the legacy pin, the pin is internally routed to
Chipset interrupt controllers. The pin that is driven is based upon the setting of the
chipset configuration registers. Specifically, the chipset configuration registers used are
the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers.
Table 5-31 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”
refers to the Hot-Plug and PME interrupt bits.
Table 5-31.MSI vs. PCI IRQ Actions
Interrupt Register
All bits 0
One or more bits set to 1
One or more bits set to 1, new bit gets set to 1
One or more bits set to 1, software clears some (but not all)
bits
One or more bits set to 1, software clears all bits
Software clears one or more bits, and one or more bits are
set on the same clock
Wire-
Mode Action
Wire inactive
Wire active
Wire active
Wire active
Wire inactive
Wire active
MSI Action
No action
Send
message
Send
message
Send
message
No action
Send
message
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